Semiconductor industry has achieved the most outstanding and fastest accomplishment within the last forty years since 1961. With the demand and evolution of technology in 3C market, the size of components will have to enter the scale of nanometer generation from micrometer to provide the improvement in speed, power, integration, and density. The feature size has advances from 250 nm, 180 nm, 130nm, and into the new 90 nm generation. ITRS forecasted that the 90 nm product will enter volume production in 2004. All global leading manufacturers are now aggressively engaging in this new manufacturing process. Companies such as Intel, IBM, TI, Toshiba, TSMC, and UMC, etc. have all started deploying 90 nm manufacturing process since 2003 in hope for the market winner. They have also all actively invested in the research of sub-90 nm manufacturing process to prepare for the forth-coming new generation.

This book discusses five technologies including Low dielectric constant material, Silicon on Insulator (SOI), MRAM, Atomic Layer Deposition (ALD), and EUV. The patent map, scientific literatures, and research projects are used for analysis to provide research topics related to nanometer electronics for the national scientific planning.. The global technological development trend is evaluated as the reference material for our country in setting policies for forward-looking technological research.

====章節目錄====
Chapter 1 Introduction
　　Section 1 Goal of Research
　　Section 2 Methods of Research
　　Section 3 Structure of Research
Chapter 2 Low Dielectric Constant Material
　　Section 1 Foreword
　　Section 2 Patent Map Analysis
　　Section 3 Scientific Literatures Analysis
　　Section 4 Research Projects Analysis
　　Section 5 Status of Leading Companies
　　Section 6 Technical Assessment
Chapter 3 Silicon on Insulator (SOI)
　　Section 1 Foreword
　　Section 2 Patent Map Analysis
　　Section 3 Scientific Literatures Analysis
　　Section 4 Research Projects Analysis
　　Section 5 Status of Leading Companies
　　Section 6 Technical Assessment
Chapter 4 Magnetic Random Access Memory (MRAM)
　　Section 1 Foreword
　　Section 2 Patent Map Analysis
　　Section 3 Scientific Literatures Analysis
　　Section 4 Research Projects Analysis
　　Section 5 Status of Leading Companies
　　Section 6 Technical Assessment
Chapter 5 Atomic Layer Deposition (ALD)
　　Section 1 Foreword
　　Section 2 Patent Map Analysis
　　Section 3 Scientific Literatures Analysis
　　Section 4 Research Projects Analysis
　　Section 5 Status of Leading Companies
　　Section 6 Technical Assessment
Chapter 6 EUV Lithography
　　Section 1 Foreword
　　Section 2 Patent Map Analysis
　　Section 3 Scientific Literatures Analysis
　　Section 4 Research Projects Analysis
　　Section 5 Status of Leading Companies
　　Section 6 Technical Assessment
Chapter 7 Conclusion
　　Section 1 Patent Map Analysis
　　Section 2 Scientific Literatures Analysis
　　Section 3 Research Projects Analysis

====表目錄====
Table 2-1 Technology Development Road Map of Low Dielectric Constant Material of ITRS
Table 3-1 Silicon wafer market price in 2003
Table 4-1 Characteristics comparison between MRAM and mainstream memory
Table 5-1 Market size and forecast of global thin film deposition equipment market.
Table 6-1 ITRS Lithography Roadmap
Table 6-2 Photolithography Technology Roadmap corrected by Intel

====圖目錄====
Figure 1-1 Structure of research
Figure 2-1 Historical patent numbers of low dielectric material
Figure 2-2 Number of Patents of low dielectric constant material published in the history
Figure 3-1 Historical number of SOI Patents
Figure 3-2 Number of Published Historical SOI Patents
Figure 3-3 Demand forecast of SOI wafers
Figure 4-1 Historical number of patents of MRAM
Figure 4-2 Number of Patents of MRAM published in the history
Figure 5-1 Global market distribution of semiconductor equipment
Figure 5-2 Historical number of patents of ALD
Figure 5-3 Number of Patents of ALD published in history
Figure 6-1 Historical number of EUV patents
Figure 6-2 Historical number of patents of EUV
Figure 6-3 shows the development schedule of LLC
Figure 6-4 EUVA development schedule
Figure 6-5 Illustration of reflective EUV optical system
Figure 6-6 Structure of EUV mask
Figure 7-1 Bubble diagram of number of patents for Nanoelectronics technology
Figure 7-2 Bubble diagram of Nanoelectronics technology for scientific literatures
Figure 7-3 Relationship between the number of research projects and amount of money invested into the Nanoelectronic technology by Taiwanese government.